Clock signals as gates from various sources are of varying quality and shapes, and do not necessarily instantaneously rise from 0.0 to 5.0 volts, even though digital. What general techniques do you use to do rising edge detection on such gate signals, or indeed square wave output of LFO's? The obvious way of checking the previous level was 0 and the current is 5 is too simplistic. How do we even know without taking a longish sample that the crest is even 5V? How do we know the trough is 0V without sampling some periods? I guess you can check for bands such as -0.1 < v < 0.1 for trough and 4.5 < v < 5.5 for crest but I am not convinced of that reasoning of my own. On very clean clock signals this works with exact checks for 0 and 5 but not on others. Andrew Macaulay's clock generator gives a very clean signal, for one.
Would appreciate help from those who actually know what they are doing in this space.
Clock signal rising edge detection
Re: Clock signal rising edge detection
Not that I know what I'm doing 
but I've been looking for a level greater than 3V to signal the onset of a trigger pulse, then waiting for the level to drop below 3V (as a trailing edge) before looking for another pulse. So far it seems to be working reasonably well, and it makes triggers out of any waveform that periodically goes over 3V.
You could get fancier, but I find working in ProcessSample() hard enough already
Cheers,
--
Terry McG
but I've been looking for a level greater than 3V to signal the onset of a trigger pulse, then waiting for the level to drop below 3V (as a trailing edge) before looking for another pulse. So far it seems to be working reasonably well, and it makes triggers out of any waveform that periodically goes over 3V.You could get fancier, but I find working in ProcessSample() hard enough already
Cheers,
--
Terry McG
Re: Clock signal rising edge detection
In my modules there is a 2.5 volt limit that has to be exceeded for a detected low high edge.
I assume, that is a common method.
I assume, that is a common method.
Re: Clock signal rising edge detection
When starting with my modules, I also tried to look for some "official" info about how to detect gates and triggers. I didn't really find anything, so I just went with a threshold of 0.1 volts, which has seemed to work fine. As long as we stay 100% in the digital domain, all clock/trigger signals are "perfect" (or at least there are no reasons why they couldn't be), so the rising and falling edges should be instantenous and switch between 0 and 5 volts just like that, without any other values between. As long as that is the case, it doesn't make much of a difference where the threshold is, if it's just somewhere between 0 and 5.
The threshold does make a difference if we use something like a sine wave as a clock source, basically shifting the offset between the wave and the detected triggers. And of course things might get more ambiguous if a VM patch receives external triggers from an analog device, where things are not always 100% perfect...
The threshold does make a difference if we use something like a sine wave as a clock source, basically shifting the offset between the wave and the detected triggers. And of course things might get more ambiguous if a VM patch receives external triggers from an analog device, where things are not always 100% perfect...